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T NT OD U C TE PR PLACEME r at E BSOL DED RE nte O rt Ce /tsc uppo m MME N RECO Technical S .intersil.co NO Data Sheet ww December 1995, Rev. E ur ct o or w conta INTERSIL 1-888
EL2071, EL2171
FN7032
150MHz Current Feedback Amplifier
The EL2071 and EL2171 are wide bandwidth, fast settling monolithic amplifiers built using an advanced complementary bipolar process. The EL2071 has a disable/enable feature which allows power down and analog multiplexing. These amplifiers use current-mode feedback to achieve more bandwidth at a given gain than conventional operational amplifiers. Designed for closed-loop gains of 7 to 50, the EL2071 and EL2171 have a 150MHz - 3dB bandwidth (AV = +20), and 2.5ns rise/fall time, while consuming only 15mA of supply current. The EL2071 consumes only 1.5mA when disabled. The wide 150MHz bandwidth and extremely linear phase (0.2dB deviation from linear at 50MHz) allow superior signal fidelity. These features make the EL2071 and EL2171 especially suited for many digital communication system applications. The EL2071's and EL2171's settling to 0.1% in 10ns and ability to drive capacitive loads make them ideal in flash A/D applications. D/A systems can also benefit from the EL2071 and EL2171, especially if linearity and drive levels are important. Elantec products and facilities comply with MIL-I-45208A, and other applicable quality specifications. For information on Elantec's processing, see Elantec document, QRA-1: Elantec's Processing, Monolithic Integrated Circuits.
Features
* 150MHz - 3dB bandwidth, AV = 20 * 10ns settling to 0.1% * VS = 5V @ 15mA * 2.5ns rise/fall times (2V step) * Overload/short-circuit protected * 7 to 50 closed-loop gain range * Low cost * EL2171 is direct replacement for CLC401 * Disable capability on EL2071
Applications
* Line drivers * DC-coupled log amplifiers * High-speed modems, radios * High-speed A/D conversion * D/A I-V conversion * Photodiode, CCD preamps * IF processors * High-speed communications * Analog multiplexing (using disable--EL2071) * Power down mode (using disable--EL2071)
Pinout
EL2171 (8-PIN PDIP, SO) TOP VIEW EL2071 (8-PIN PDIP, SO) TOP VIEW
Ordering Information
PART NUMBER EL2171CN EL2171CS EL2071CN EL2071CS TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PACKAGE 8-Pin PDIP 8-Pin SO 8-Pin PDIP 8-Pin SO PKG. NO. MDP0031 MDP0027 MDP0031 MDP0027
Manufactured under U.S. Patent No. 4,893,091
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners.
EL2071, EL2171
Absolute Maximum Ratings (TA = 25C)
Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V
(Output Current Output is short-circuit protected to ground, however,maximum reliability is obtained if IOUT does not exceed 70mA.)
Common Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature Ceramic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175C Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-60C to +150C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Open-Loop DC Electrical Specifications
PARAMETER VOS DESCRIPTION Input Offset Voltage
VS = 5V, RL = 100, unless otherwise specified TEST CONDITIONS TEMP 25C TMIN, TMAX MIN TYP 3 MAX 6 10 20 10 50 20 36 100 10 200 30 46 40 100 50 40 55 50 15 1.5 100 50 0.5 0.2 100 200 0.5 2.5 2 50 35 3.2 3 3.5 70 2.8 2.0 2.5 0.3 200 21 3.0 200 UNITS mV mV V/C A A nA/C A A A nA/C dB dB mA mA k k pF k pF V V mA mA V V
TC VOS +IIN
Average Offset Voltage Drift +Input Current
(Note 1)
All 25C, TMAX TMIN
TC (+IIN) -IIN
Average +Input Current Drift -Input Current
(Note 1)
All 25C TMIN TMAX
TC (-IIN) PSRR CMRR IS ISOFF +RIN
Average -Input Current Drift Power Supply Rejection Ratio Common-Mode Rejection Ratio Supply Current--Quiescent Supply Current--Disabled +Input Resistance
(Note 1) (Note 2)
All All All
No Load EL2071 (Note 3)
All All 25C, TMAX TMIN
CIN ROUT ROUTD COUTD CMIR
Input Capacitance Output Resistance (DC) Output Resistance (DC) Output Capacitance (DC) Common-Mode Input Range Output Current EL2071 Disabled EL2071 Disabled (Note 4)
All All All All 25C, TMAX TMIN 25C, TMAX TMIN
IOUT
VOUT
Output Voltage Swing
No Load
25C, TMAX TMIN
2
EL2071, EL2171
Open-Loop DC Electrical Specifications
PARAMETER VOUTL ROL ILOGIC VDIS DESCRIPTION Output Voltage Swing Transimpedance Pin 8 Current @+5V Minimum Pin 8 V to Disable EL2071 EL2071 VS = 5V, RL = 100, unless otherwise specified (Continued) TEST CONDITIONS RL = 100 TEMP 25C 25C All 25C TMIN TMAX VEN IDIS IEN NOTES: 1. Measured from TMIN to TMAX. 2. PSRR is measured at VS = 4.5V and VS = 5.5V. Both supplies are changed simultaneously. 3. Supply current when disabled is measured at the negative supply. 4. Common-Mode Input Range for Rated Performance. Maximum Pin 8 V to Enable Minimum Pin 8 I to Disable Maximum Pin 8 I to Enable EL2071 EL2071 EL2071 All All All 750 35 4.3 4.0 4.6 0.7 V A A V MIN 3.2 250 TYP 3.4 1000 500 750 MAX UNITS V V/mA A
Closed-Loop AC Electrical Specifications
PARAMETER DESCRIPTION FREQUENCY RESPONSE SSBW -3dB Bandwidth (VOUT < 2.0 VPP)
VS = 5V, RF = 1.5k, AV = +20, RL = 100 unless otherwise specified TEST CONDITIONS TEMP MIN TYP MAX UNITS
25C TMIN TMAX
100 100 70 65 55
150
MHz MHZ MHz
LSBW
-3dB Bandwidth (VOUT < 5.0 VPP)
25C, TMIN TMAX
100
MHz MHz
GAIN FLATNESS GFPL Peaking VOUT < 2.0 VPP Peaking VOUT < 2.0 VPP Rolloff VOUT < 2.0 VPP < 25MHz 25C TMIN, TMAX > 25MHz 25C TMIN, TMAX < 50MHz 25C TMIN TMAX LPD Linear Phase Deviation VOUT < 2.0 VPP < 50MHz 25C, TMIN TMAX 0.2 0.2 0.0 0.0 0.1 0.1 0.2 0.2 1.0 1.0 1.3 1.0 1.5 dB dB dB dB dB dB dB
GFPH
GFR
TIME-DOMAIN RESPONSE tR1, tF1 Rise Time, Fall Time 2.0V Step 25C, TMIN TMAX tR2, tF2 Rise Time, Fall Time 5.0V Step 25C, TMIN TMAX tS Settling Time to 0.1% 2.0V Step All 10 5 2.5 3.5 5 7 8 15 ns ns ns ns ns
3
EL2071, EL2171
Closed-Loop AC Electrical Specifications
PARAMETER OS SR Overshoot Slew Rate DESCRIPTION VS = 5V, RF = 1.5k, AV = +20, RL = 100 unless otherwise specified (Continued) TEST CONDITIONS 2.0V Step TEMP All 25C, TMIN TMAX DISTORTION HD2 2nd Harmonic Distortion @20MHz 3rd Harmonic Distortion @20MHz 2VPP 25C TMIN, TMAX 2VPP 25C TMIN TMAX EQUIVALENT INPUT NOISE NF Noise Floor >100kHz 25C TMIN TMAX INV Integrated Noise 100kHz to 200MHz 25C TMIN TMAX DISABLE/ENABLE PERFORMANCE--EL2071C TOFF TON ISO VOUT = 2 VPP Disable Time to >40dB Enable Time Off Isolation 20MHz 20MHz All All All 50 70 40 55 200 100 ns ns dB 35 -158 -155 -155 -154 50 50 55 dBm (1Hz) dBm (1Hz) dBm (1Hz) V V V -60 -45 -35 -35 -50 -50 -45 dBc dBc dBc dBc dBc 800 700 MIN TYP 0 1200 MAX 10 UNITS % V/s V/s
HD3
4
EL2071, EL2171 Typical Performance Curves
Non-Inverting Frequency Response Inverting Frequency Response Frequency Response for Various RLs
Open-Loop Transimpedance Gain and Phase
Frequency Response, AV = -1, RF = 2.5k
Equivalent Input Noise
Single Power Supply Rejection Ratio
Common Mode Rejection Ratio (AV = +20)
Recommended RS vs Load Capacitance
5
EL2071, EL2171 Typical Performance Curves (Continued)
2nd and 3rd Harmonic Distortion 2-Tone 3rd Order Intermodulation Intercept
Pulse Response AV = +20
Pulse Response AV = +20
Forward and Reverse Gain during Disable--EL2071
Disabled Attenuation vs Time for Various Output Levels--EL2071
6
EL2071, EL2171 Typical Performance Curves (Continued)
Disable Response--EL2071 Enable Response--EL2071
8-Pin SO Maximum Power Dissipation vs Ambient Temperature
8-Pin Plastic DIP Maximum Power Dissipation vs Ambient Temperature
7
EL2071, EL2171 Equivalent Circuit
Burn-In Circuit
flowing into the inverting input in the steady-state (nonslewing) condition is very small. Therefore we can still use op-amp assumptions as a firstorder approximation for circuit analysis, namely that: 1.The voltage across the inputs is approximately 0V. 2.The current into the inputs is approximately 0mA.
Resistor Value Selection and Optimization
The value of the feedback resistor (and an internal capacitor) sets the AC dynamics of the EL2071/EL2171. The nominal value for the feedback resistor is 1.5k, which is the value used for production testing. This value guarantees stability. For a given closed-loop gain the bandwidth may be increased by decreasing the feedback resistor and, conversely, the bandwidth may be decreased by increasing the feedback resistor. Reducing the feedback resistor too much will result in overshoot and ringing, and eventually oscillations. Increasing the feedback resistor results in a lower -3dB frequency. Attenuation at high frequency is limited by a zero in the closed-loop transfer function which results from stray capacitance between the inverting input and ground. Consequently, it is very important to keep stray capacitance to a minimum at the inverting input.
ALL PACKAGES USE THE SAME SCHEMATIC.
Applications Information
Theory of Operation
The EL2071/EL2171 have a unity gain buffer from the noninverting input to the inverting input. The error signal of the EL2071/EL2171 is a current flowing into (or out of) the inverting input. A very small change in current flowing through the inverting input will cause a large change in the output voltage. This current amplification is called the transimpedance (ROL) of the EL2071/EL2171 [VOUT = (ROL) * (-IIN)]. Since ROL is very large, the current
8
EL2071, EL2171
Capacitive Feedback
The EL2071/EL2171 rely on their feedback resistor for proper compensation. A reduction of the impedance of the feedback element results in less stability, eventually resulting in oscillation. Therefore, circuit implementations which have capacitive feedback should not be used because of the capacitor's impedance reduction with frequency. Similarly, oscillations can occur when using the technique of placing a capacitor in parallel with the feedback resistor to compensate for shunt capacitances from the inverting input to ground. the EL2071 is connected in a gain of +7 configuration and is disabled while the analog bus is driven externally to +5V. Pin 2 is consequently at +0.71V, and if VIN is driven to -5V, then 5.71V appears between pins 3 and 2. Internally, this voltage appears across a forward biased VBE in series with a reverse biased VBE and is past the threshold for zenering the reverse biased VBE. In a typical application, a 50 or 75 terminating resistor from pin 3 to ground will prevent pin 3 from approaching -5V.
Printed Circuit Layout
As with any high frequency device, good PCB layout is necessary for optimum performance. Ground plane construction is a requirement, as is good power-supply bypassing close to the package. The inverting input is sensitive to stray capacitance, therefore connections at the inverting input should be minimal, close to the package, and constructed with as little coupling to the ground plane as possible. Capacitance at the output node will reduce stability, eventually resulting in peaking, and finally oscillation if the capacitance is large enough. The design of the EL2071/EL2171 allow a larger capacitive load than comparable products, yet there are occasions when a series resistor before the capacitance may be needed. Please refer to the graphs to determine the proper resistor value needed.
Using the EL2071 as a Multiplexer
An interesting use of the enable feature is to combine several amplifiers in parallel with their outputs in common. This combination then acts similar to a MUX in front of an amplifier. A typical circuit is shown. The series resistance at each output helps to further increase isolation between amplifiers. When the EL2071 is disabled, the DC output impedance is > 100k in parallel with 2pF capacitance. To operate properly, the decoder that is used must have a VOH > (VS+) - 0.4V with IOH = 750A, and should be connected to the same power supply as the EL2071.
Disable/Enable Operation for EL2071
The EL2071 has a disable/enable control input at pin 8. The device is enabled and operates normally when pin 8 is left open or returned to ground. When the voltage at pin 8 is brought to within 0.4V of pin 7 (VS+), the EL2071 is disabled. The output becomes a high impedance, the inverting input is no longer driven to the positive input voltage, and the supply current is reduced to less than 2.2.mA. There are internal resistors which limit the current at pin 8 to a safe level (~ 500A) if pin 8 is shorted to either supply. Typically, analog and digital circuits should have separate power supplies. This usually leads to slight differences between the power supply voltages. The EL2071's disable feature is dependent on the voltage at pins 8 and 7. Therefore, to operate the disable feature of the EL2071 dependably over temperature, it is recommended that the logic circuitry which drives pin 8 of the EL2071 operate from the same +5V supply as the EL2071 to avoid voltage differences between the digital and analog power supplies. Since VDIS is temperature dependent, it is recommended that 5V CMOS logic (with a VOH > 4.6V sourcing > 750A over temperature) be used to drive the disable pin of the EL2071. When disabled, (as well as in enabled mode), care must be taken to prevent a differential voltage between the + and inputs greater than 5.0V. For example, in the figure below, 9
EL2071, EL2171 EL2071 Macromodel
* Revision A. March 1992 * Enhancements include PSRR, CMRR, and Slew Rate Limiting * Connections: +input * | -input * | | +Vsupply * | | | -Vsupply * | | | | output * ||||| .subckt M2071 3 2 7 4 6 * * Input Stage * e1 10 0 3 0 1.0 vis 10 9 0V h2 9 12 vxx 1.0 r1 2 11 2 l1 11 12 1nH iinp 3 0 10A iinm 2 0 10A * * Slew Rate Limiting * *h1 13 0 vis 1K h1 13 0 vis 600 r2 13 14 100 d1 14 0 dclamp d2 0 14 dclamp * * High Frequency Pole * *e2 30 0 14 0 0.00166666666 e2 30 0 14 0 0.001 13 30 17 1.0H c5 17 0 0.1pF r5 17 0 500 * * Transimpedance Stage * g1 0 18 17 0 1.0 rol 18 0 1Meg cdp 18 0 0.88pF * * Output Stage * q1 4 18 19 qp q2 7 18 20 qn q3 7 19 21 qn q4 4 20 22 qp r7 21 6 2 r8 22 6 2 ios1 7 19 2.5mA ios2 20 4 2.5mA * * Supply Current * ips 7 4 9mA * * Error Terms *
10
EL2071, EL2171 EL2071 Macromodel
(Continued)
ivos 0 23 3mA vxx 23 0 0V e4 24 0 3 0 1.0 e5 25 0 7 0 1.0 e6 26 0 4 0 1.0 r9 24 23 316 r10 25 23 562 r11 26 23 562 * * Models * .model qn npn (is=5e-15 bf=500 tf=0.05nS) .model qp pnp (is=5e-15 bf=500 tf=0.05nS) .model dclamp d(is=1e-30 ibv=1pA bv=3.5 n=4) .ends
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